CEM
3D Electromagnetics, powered by Palace
Designing Transmon Charging Energy Through Capacitance Extraction
- Quantum Computing
- Semiconductors
- RF & Microwave
What This Simulation Does
The transmon_capacitance example performs an electrostatic extraction of the Maxwell capacitance matrix for a transmon qubit's electrode pads sitting on a dielectric substrate. The pad–pad and pad–ground capacitances directly set the qubit charging energy EC — the first and most fundamental design knob in superconducting-qubit hardware.
- Laplace solve — Palace solves ∇·(ε∇V) = 0 for the scalar potential, energizing one terminal (pad) at a time and reading the surface charge to build the full self- and mutual-capacitance matrix
- Charging energy follows directly as EC = e2/(2CΣ), where CΣ is the total capacitance seen by the Josephson junction
- High-order finite elements (order 2) on a substrate + vacuum geometry meshed in micrometers, resolving the sharp field concentrations at pad edges that dominate the capacitance
Key Parameters
- Problem type: Electrostatic, length unit L0 = 1 μm
- Materials: substrate (εr = 10.3, sapphire/silicon class) and vacuum (εr = 1.0)
- Boundaries: ground plane (V = 0), Pad 1 = Terminal 1, Pad 2 = Terminal 2
- Postprocessing: region energy participation + SurfaceFlux (electric) → terminal charge
- Solver: conjugate gradient (CG) + BoomerAMG preconditioner, tolerance 1e-8, GPU device
The core transferable physics: a set of conductors on/near a dielectric forms a capacitance network. Solving Laplace's equation once per terminal recovers the entire matrix. What changes across applications is the geometry (qubit pads, MEMS combs, IC interconnect, sensor electrodes) and what the capacitance controls — qubit frequency, sensor sensitivity, or signal-line delay.
What Makes This Capability Unique
Full-wave-grade field accuracy for a static problem.
Order-2 elements resolve the edge-singular fields at pad corners that dominate C. Analytic and 2D approximations miss these, giving EC errors that shift the qubit frequency by hundreds of MHz.
Full matrix from one solve per terminal.
Energizing each pad in turn yields self- and mutual-capacitances in a single job — the exact lumped network a circuit designer needs, no hand-tuning.
Energy participation for free.
Region energies quantify how much field lives in the substrate vs vacuum — the same participation ratios that feed loss and coherence budgets.
Seconds on cloud GPUs.
A CG + BoomerAMG solve of this size runs in seconds, making pad-geometry sweeps of dozens of layouts a same-day exercise.
Domain Applications
Select a domain to see how this simulation applies, with industry-specific scenarios and ROI.
The Problem
A transmon qubit's frequency is set by two energies: the Josephson energy EJ (from the junction) and the charging energy EC (from the total island capacitance). EC is almost entirely geometric — it is fixed by the size, shape, and spacing of the capacitor pads and their coupling to ground. Getting EC wrong by even a few percent moves the qubit frequency by hundreds of MHz, pushing it into collisions with neighbors, readout resonators, or two-level-system (TLS) defects.
Frequency collisions are the dominant yield killer for fixed-frequency transmon processors. On a large chip, the probability that all qubits land in their allowed windows falls off steeply with qubit count, and a single collision can render a two-qubit gate unusable. Fabrication rounds cost $50K–$250K and 6–12 weeks each, so a design that lands frequencies on the first pass is worth an entire tape-out cycle.
Accurate capacitance extraction is the bridge between a CAD layout and the predicted qubit spectrum. It lets designers place every qubit in its target window before committing to fabrication, and it feeds the participation ratios used to budget dielectric loss and coherence.
Applications
| Application | How this simulation maps |
|---|---|
| Qubit frequency targeting | CΣ from the matrix gives EC = e²/2CΣ; combined with EJ it predicts the qubit frequency to place it in an allowed window |
| Pad geometry optimization | Sweep pad size/gap and re-extract C to hit a target EC without changing the junction |
| Collision-aware layout | Per-qubit C extraction across the chip predicts the full frequency map and flags collisions pre-fab |
| Coherence budgeting | Substrate vs vacuum energy participation feeds surface-loss and TLS coherence estimates |
Quantifiable Business Value
Scenario: A quantum-hardware team tapes out a fixed-frequency transmon processor. Without simulation-driven frequency targeting, first-pass yield (all qubits in-window) is 40% and typically requires 2.5 fabrication iterations. Capacitance-informed design raises first-pass yield and cuts iterations to 1.3.
Beyond direct fab savings, halving the design schedule accelerates the processor roadmap by months per generation — the difference between leading and trailing in a field where qubit count doubles yearly.
Recommended Next Steps
Extract your own layout
Swap in your pad/electrode geometry and substrate permittivity, then run the electrostatic solve to get the full capacitance matrix and EC.
Sweep the geometry
Vary pad size, gap, and ground spacing to map C and land on a target charging energy or parasitic budget.
Build the full network
Combine with qubit_coupler (mutual capacitance) and readout_lambda4 (resonator) to assemble the complete multi-qubit electromagnetic model.
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