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The qubit_coupler example is an electrostatic extraction of the mutual capacitance between two neighboring superconducting qubit islands on a dielectric substrate. The island-to-island capacitance C12 sets the static (capacitive) coupling budget between the qubits — the parameter that governs two-qubit gate rates and unwanted crosstalk.
- Laplace solve per terminal — each island is held at a fixed potential; energizing one at a time gives the full capacitance matrix, whose off-diagonal entry C12 is the mutual capacitance that couples the qubits
- SurfaceFlux (electric) on each island yields the terminal charge from which the matrix is assembled
- Order-2 elements on substrate + vacuum meshed in micrometers, resolving the fringing fields between islands that dominate C12
- Problem type: Electrostatic, length unit L0 = 1 μm
- Materials: substrate (εr = 10.3) and vacuum (εr = 1.0)
- Boundaries: ground plane (V = 0), Island 1 = Terminal 1, Island 2 = Terminal 2
- Postprocessing: SurfaceFlux (electric) on each island → terminal charge, C-matrix
- Solver: CG + BoomerAMG preconditioner, tolerance 1e-8, GPU device
The core transferable physics: the mutual capacitance between two conductors is a purely geometric quantity governing how strongly they are electrostatically linked. Whether the conductors are qubit islands, coupled transmission lines, sensor electrodes, or adjacent IC nets, the same off-diagonal capacitance sets the coupling — desired (gates, sensing) or parasitic (crosstalk).
Mutual capacitance lives almost entirely in the fringe field between islands. High-order FEM captures it where parallel-plate approximations fail by 2–3×.
C12 maps straight into the qubit–qubit coupling strength g, so designers dial the gate rate directly from geometry.
The same extraction reveals unwanted coupling to spectator qubits — the number that limits gate fidelity on a crowded chip.
Seconds per solve means island-spacing sweeps to hit a target C12 are a same-day study, not a fab cycle.
Select a domain to see how this simulation applies, with industry-specific scenarios and ROI.
Two-qubit gates are the throughput bottleneck and the dominant error source in superconducting quantum processors. The gate rate is set by the coupling strength g between qubits, which for capacitively-coupled architectures is fixed by the mutual capacitance C12. Too little coupling and gates are slow (decoherence-limited fidelity); too much and always-on ZZ crosstalk corrupts idle qubits.
Because C12 is geometric, it must be right at design time. An error moves g by the same fraction, detuning tunable couplers or leaving fixed couplers off-spec — a defect that only appears after a $50K–$250K, 6–12 week fabrication round.
Accurate mutual-capacitance extraction lets teams set the coupling budget for every qubit pair and quantify residual crosstalk to spectators before committing silicon.
| Application | How this simulation maps |
|---|---|
| Two-qubit gate rate design | C12 → coupling g → gate time; tune island spacing to a target gate speed |
| Tunable-coupler layout | Direct and coupler-mediated capacitances set the on/off ratio of a tunable coupler |
| Crosstalk / ZZ budgeting | Residual mutual capacitance to spectators predicts always-on ZZ error |
| Isolation & shielding | Ground-strap and island-shape sweeps minimize unwanted coupling |
Scenario: A processor team designs coupler geometries empirically, needing 2.2 fab iterations to hit the coupling spec. Mutual-capacitance extraction reduces this to 1.2.
Lower ZZ crosstalk from optimized coupling also raises two-qubit gate fidelity — directly improving the quantum volume that defines the processor's market value.
Extract your coupling
Load your island/electrode pair and substrate, run the electrostatic solve, and read C12 from the matrix.
Sweep the spacing
Vary island separation and shape to hit a target mutual capacitance and minimize crosstalk to spectators.
Close the network
Combine with transmon_capacitance (charging energy) and readout_lambda4 (readout) for the full multi-qubit model.
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