
3D Electromagnetics, powered by Palace
The coaxial_open example is a time-domain (transient) simulation of a coaxial transmission line driven by a pulse and terminated in a open-circuit. Palace propagates the incident pulse down the line and captures the reflected wave, whose amplitude and sign are set by the termination's reflection coefficient Γ = +1.
- Open-circuit termination — with the line left open, the incident pulse reflects fully and in phase (Γ = +1); the voltage at the open end momentarily doubles
- Positive reflection — this is one of the two full-reflection extremes, the classic signature of a broken or unterminated line on a TDR trace
- TEM propagation on the coaxial line with the incident and reflected pulses cleanly separated in time, exactly as a time-domain reflectometer (TDR) would measure
- Problem type: Transient (time domain), coaxial line, 50 Ω characteristic impedance
- Excitation: pulsed lumped port launching a TEM wave
- Termination: open-circuit (reflection coefficient Γ = +1)
- Boundaries: outer/inner conductor = PEC; feed via lumped port
- Output: time-resolved voltage/field, incident and reflected pulse trace
The core transferable physics: whenever a signal meets an impedance discontinuity, part of it reflects with a coefficient Γ = (ZL − Z₀)/(ZL + Z₀). The matched, open, and short cases are the three reference points (Γ = 0, +1, −1) that anchor all signal-integrity and TDR analysis. Any real discontinuity — a connector, via, stub, or fault — sits between these extremes.
An open circuit reflects the entire pulse in phase, doubling the end voltage — the unmistakable TDR signature of an open, broken, or unterminated interconnect.
The transient solve reproduces exactly what a TDR instrument sees, so simulated and measured waveforms can be compared point-for-point.
The 3D field solution captures the true geometry of the line and its termination — no idealized circuit approximation.
Known reflection coefficients make this a trusted calibration case for the transient solver and for engineers' intuition.
Select a domain to see how this simulation applies, with industry-specific scenarios and ROI.
Every high-speed interconnect — cables, connectors, vias, board traces — is a transmission line, and every impedance discontinuity reflects part of the signal. Reflections degrade the eye diagram, cause bit errors, and radiate EMI. As edge rates get faster, even small discontinuities matter.
Diagnosing these problems on hardware with a TDR is a lab exercise that comes late, after the board is built. A discontinuity that fails signal-integrity sign-off can force a respin costing $50K–$300K and weeks.
Transient full-wave simulation predicts the reflection behavior — the same waveform a TDR would show — before hardware exists.
| Application | How this simulation maps |
|---|---|
| Interconnect TDR | Reflected pulse locates and sizes impedance discontinuities |
| Connector / via design | Termination reflection quantifies discontinuity severity |
| Impedance verification | Matched-case reference confirms 50 Ω design intent |
Scenario: A high-speed board team spins 18 designs/year, with 1 in 3 needing a respin after a reflection/SI failure. Transient pre-analysis cuts respins to 1 in 12.
Each avoided respin also protects the launch schedule — often the larger cost in a competitive product cycle.
Model your line
Load your coax/interconnect geometry and termination, launch a pulse, and read the reflected waveform.
Introduce discontinuities
Add connectors, steps, or faults and watch the TDR trace to locate and size each reflection.
Compare the references
Contrast coaxial_matched (Γ = 0), coaxial_open (Γ = +1), and coaxial_short (Γ = −1) to build intuition for real discontinuities.
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